13

Operation scheduling for the synthesis of false loop free circuits

Year:
2007
Language:
english
File:
PDF, 294 KB
english, 2007
26

Power-mode-aware buffer synthesis for low-power clock skew minimization

Year:
2016
Language:
english
File:
PDF, 1.92 MB
english, 2016
34

Module binding for low power clock gating

Year:
2008
Language:
english
File:
PDF, 207 KB
english, 2008
49

An ILP approach to surge current minimization in high-level synthesis

Year:
2009
Language:
english
File:
PDF, 293 KB
english, 2009